1. Field of the Invention
The present invention relates to semiconductors, and more particularly to structures that improve on the breakdown voltage between source and drain in field effect transistors and other semiconductors.
2. Description of the Prior Art
Sharp edges and especially points in conductors have long been known to collect charges that can become high enough to result in a current that will jump a vacuum-surface barrier. This phenomenon is usefully employed in microelectronic vacuum field emission devices that promote an electron flow from a non-heated semiconductor cathode. In field emission devices, anode and gate voltages as low as 100 volts are enough to result in emission from the micron sized radius at the apex of cone-shaped cathodes.
However, in other devices, the charge concentrations in small radius tips of conductors can lead to undesirable consequences. Considering high voltage field effect transistors (FET), they have a source, a drain, and a channel between them. If the source or drain is not round, charges can concentrate in any projections facing the direction of the opposite electrode. In a FET, charge concentrations can lead to reduced breakdown voltage ratings. For a general background on this subject, refer to M. Amato, "Reduced Electric Field Crowding at the Fingertips of Lateral DMOS Transistors," Proceedings of the Electrochemical Society Meeting, May 1989, pp. 161-162; and Hamza Yilmaz, "Modeling and Optimizing of Lateral High Voltage IC Devices to Minimize 3-D Effects," Proceedings of the Electrochemical Society Meeting, May 1989, pp. 155-156. Every channel will have a finite amount of voltage standoff to breakdown currents. The electric field concentrations will be greatest at any sharp tips in the source and/or drain. To combat this, the prior art has rounded off wide pointed structures. An example of this is shown in a FET 10 in FIGS. 1 and 2, which illustrate a portion of a FET.
FET 10 has a source electrode 12 in the shape of a line segment and a horse shoe-shaped drain electrode 14 that encircles one end of the source electrode 12. Electrode 12 has a diffusion 16 and electrode 14 has a diffusion 18 in a substrate 20. A polysilicon gate electrode 22 is insulated from the underlying silicon channel by a gate silicon oxide 24. In the prior art, such as FET 10, a channel comprising an n.sup.- drift region 26 uniformly surrounds both sides and the one end of the source 12 and has a p-top layer 27 that tops an extended drain structure. The width of the channel is roughly equal all around the source 12. The channel current could therefore be expected to be equally distributed. It has been observed that breakdown current flow occurs at the small radius tip of the source when a device is over-voltage stressed, e.g., a tip 28 in FIG. 1. To counteract this, prior art devices deliberately increase the width of the source, in order to increase the radius of the tip 12. Though this measure tends to improve the breakdown voltage rating, it also requires that the transistor be much larger. Typically, the n-well 18 radius near the gate will be about fifty microns with a drift 26 length of eighty microns for a 1,000 volt rated device.
With the current trend toward smaller devices, the prior art method of increasing the tip radii is unacceptable.